In recent years, as a semiconductor device has been downsized, a double patterning technology has been developed. The double patterning technology is a technology for forming a minute circuit pattern, in which the circuit pattern to be formed is separated into two parts followed by exposure. As the double patterning technology, a method of forming a minute pattern using a sidewall as an etching mask has been known (see Japanese Patent Kokai Publication No. JP2001-156283A (Patent Document 1), for example).
FIGS. 21A to 22C illustrate schematic flowcharts (including figures corresponding to FIGS. 1(a)-(f) of Patent Document 1) to explain a method of forming a minute pattern according to a background art. In FIGS. 21A to 22C, (Z) figures on a left side are schematic top views of a semiconductor device. At the upper left of FIG. 21A, directions in the (Z) figures are shown. In the (Z) figures, a lateral (horizontal) direction corresponds to X axis, a vertical direction corresponds to Y axis, and a perpendicular direction to the surface corresponds to Z axis. The (X) figures at the central are schematic cross-sections along an X-X line of the (Z) figure on the left side, and the (Y) figures on the right side are schematic cross-sections along a Y-Y line of the (Z) figure. In FIG. 21A, a semiconductor substrate 91, a processing target layer 92 and a first dielectric interlayer 93 are stacked. Here, the background art will be explained giving an example of a method of forming the minute pattern of the processing target layer 92.
First, the first dielectric interlayer 93 is etched to make openings 94 on both sides, and therefore a dielectric interlayer line 93a is formed (FIG. 21B). Next, an etching mask layer 95 is formed on the processing target layer 92 and the dielectric interlayer line 93a (FIG. 21C). Next, sidewalls of the dielectric interlayer line 93a are formed by etching-back of the etching mask layer 95 (FIG. 21D). These sidewalls serve as etching masks 95a along side surfaces of the dielectric interlayer line 93a. Next, the dielectric interlayer line 93a between two etching masks 95a is removed by etching (FIG. 22A). Next, minute patterns 92a are formed by etching the processing target layer 92 using the etching masks 95a as masks (FIG. 22B). Lastly, the etching masks 95a are removed, and a second dielectric interlayer 96 is formed around the minute patterns (FIG. 22C).
The following analysis is given in view of the present disclosure.
In the method illustrated in FIGS. 21-22, as described in Patent Document 1, the etching mask 95a exists on the minute pattern 92a in the state illustrated in FIG. 22B. Because the thickness of the minute pattern 92a is equal to the thickness of the processing target layer 92, and the etching mask 95a is formed as the sidewall of the first dielectric interlayer 93, a total thickness t of the minute pattern 92a and etching mask 95a depends on a thickness of each layer (200 nm of the total thickness t, for example). Accordingly, the narrower the width w of the minute pattern 92a becomes (10 nm-30 nm of the width w, for example), the higher an aspect ratio (7 to 20 in the above example of the thickness t and width w, for example) of the combination pattern of the minute pattern 92a and etching mask 95a becomes.
Therefore, there is a probability that a combination pattern of the minute pattern 92a and the etching mask 95a becomes unstable so as to fall down. This may happen also in a state where only the etching mask is present as illustrated in FIG. 22A.